TSMC Advances Panel-Level Packaging Technology; CoPoS Pilot Line Expected to Be Completed in June

According to *The Business Times*, TSMC’s CoPoS (Chip-on-Panel-on-Substrate) pilot production line began delivering equipment to its R&D team in February, with the entire line expected to be fully operational by June.

The Business Times noted that the rise of CoPoS technology highlights the industry’s shift toward panelization, viewing it as a key solution to advanced packaging bottlenecks: as the photoresist dimensions of AI chips continue to increase—for example, NVIDIA’s Rubin GPU is now 5.5 times larger than before—a standard 12-inch wafer can now accommodate only seven units, and in some cases, as few as four. The report states that the square panel format can significantly improve utilization and throughput, with the long-term goal of replacing silicon interposers with glass substrates.

According to the Business Times, with TSMC’s CoPoS pilot production line expected to be completed by mid-year, the industry generally anticipates that mass production will gradually begin between 2028 and 2029. However, supply chain sources cited in the report also cautioned that as substrate sizes increase, warpage issues intensify, becoming one of the biggest obstacles to large-scale production.

Meanwhile, the Central News Agency noted that TSMC may establish its first CoPoS pilot line in Chiayi and plans to conduct mass production at that site, with expectations of further integrating CoPoS, SoIC (System-on-Chip), and WMCM (Wafer-Level Multi-Chip Module) capabilities.

CNA reported that TSMC also plans to convert existing 8-inch wafer fabs in Taiwan into advanced packaging facilities, while current back-end fabs will support production of cutting-edge 2nm processes.